• Outstanding theoretical background in Signal Integrity and electromagnetic compatibility techniques/tools – Experts of High-Speed-Digital and RF Design-House :

•  Developers of Virtual-EMI-Lab for advanced EMC debug/analysis using HFSS, FDTD (Agilent-EMpro) & Si-waves, Momentum & CST-uWave Studio with GPGPU/CUDA-acceleration. Developed combined Simulation and Near-/far-field scanning to define on-chip/on-board/Cables EMI suppressors during the early design stages of chip & PCB development. 

•   Unique SI/PI/EMC pre-layout and post-layout simulation workflow  for accurate ‘what-if’ analysis of critical HSD interfaces for maximum channel performance with minimum cost of PCBs (low-layer counts) and BOMs. Experts in Trading-off between Cost, Performance and Power. 

•  Developers of Advanced frequency domain (FD) techniques for optimization of Signal-Quality and PDN for interconnects of high speed digital systems correlating worst case corners with lab and VNA measurements.

•  Expertise in Hspice, Cougar (Intel spice tool), TIspice (TI spice tool), Cadence (SprectraQuest suit), Mentor-Hyperlynx,  Sigrity-Power-SI and Optimize-PI, CST-uWave Studio, ADS (Agilent) and HFSS (Annsoft) modeling/analysis with IBIS and/or transistor level models.

•  Experts in AC timing  analysis for synchronous and asynchronous busses such as  DDR1/2/3/4, GDDR3/5, PCI-e, and Ethernet, GMSL, USB, SGMII/RGMII, SPI/QSPI, eMMC. 

•  Fluent with CST-uWave Studio, CST- PCBS & Momentum for extracting accurate 3D models of interconnects, and packaging with non-ideal power delivery for SSO simulations.  

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